Method of producing a multi-layered wiring board

ABSTRACT

Method of producing a multi-layered wiring board comprising the steps of subjecting the photosensitive resin to exposure- and development-treatment to form the holes having a predetermined size and shape; depositing and forming the curable resin to the insulating layer having the holes formed therein in such a manner as to bury the holes, and conducting heat-treatment to form the cured thin film of the curable resin on the surface of the insulating layer; and so removing the curable resin as to leave the cured thin film to obtain the via-holes having the reduced opening size by the cured thin film.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method of producing amulti-layered wiring board and more particularly to the method ofproducing a multi-layered wiring board by laminating serially conductorlayers and insulating layers.

[0003] 2. Description of the Background Art

[0004] A finer pattern and a multi-layered structure have been employedrapidly in printed wiring boards for mounting semiconductor devices asthe electronic appliances have become smaller in size and weight andhigher in operation speed and function. Via-holes that establishelectric conduction between upper and lower circuits at arbitrarypositions are not easily formed in multi-layered wiring structures onpress laminated boards. For this reason, a build-up system thatlaminates serially and alternately insulating layers and conductorlayers to form a multi-layered wiring board has been employed instead.

[0005] The multi-layered wiring board by the build-up system hasgenerally the structure in which via-holes of upper layers and via-holesof lower layers do not overlap with one another. To achieve a highersignal speed, however, a circuit pattern must be as short as possible,and a “via-on-via structure”, in which the via-holes of the upper layersare stacked on the via-holes of the lower layers, has drawn anincreasing attention.

[0006] A process for forming the via-holes is described in the followingreference, for example:

[0007] “High Density Build-up Technology for Flip Chip Application”,Mottoi Asai, p200, IEMT/IMC Proceedings 1999

[0008] This technology uses a photo via-hole process. The conventionalformation method of via-on-via by the build-up system will be explainedwith reference to this technology.

[0009]FIG. 6 shows a basic shape of a core substrate 3 for forming themulti-layered wires. A wiring pattern 20 a having lines 40 and lands 50as a first conductor layer is formed beforehand by photolithography orlike means on the core substrate 3. In the example shown, a land(via-hole) pitch is 800 μm and a land diameter (LD) is 250 μm. Two linesare extended at 100 μm L/S (line/space) between the lands.

[0010]FIG. 8 shows the conventional process for forming via-on-via onthe core substrate 3. In the drawing, reference numeral 1 denotes afirst insulating layer having a photosensitive negative type resist, forexample. Reference numeral 11 denotes an insulating layer pattern formedwhen the first insulating layer 1 is exposed and developed. Referencenumeral 8 denotes a via for holding electric conduction between upperlayer lands and lower layer lands. Reference numeral 60 denotes aphoto-mask formed by vacuum depositing a metal such as Cr to portionscorresponding to lands represented by 50. An arrow 70 representsultraviolet rays that are used for exposure, and reference numeral 80denotes a via-hole.

[0011] Suffixes a, b, c and d will be used to identify the first,second, third and fourth layers when a member having the same functionis formed in a plurality of layers.

[0012] In the first step 1, a first insulating layer 1 a of the firstlayer is spin-coated uniformly to a thickness of 5 to 70 μm on the coresubstrate 3, for example. Pre-baking is then conducted at 70 to 150° C.to evaporate away an excessive solvent contained in the first insulatinglayer 1 a.

[0013] In the step 2, ultraviolet rays are irradiated to expose thefirst insulating layer 1 a with a photo-mask 60 a. Reaction componentssuch as acids and radicals occur at the portions irradiated by theultra-violet rays 70 a, forming a cross-linked structures.

[0014] In the step 3, development is conducted. When the firstinsulating layer 1 a is washed with a developing solution, the portionsnot irradiated with the ultra-violet rays 70 a are dissolved away. Inconsequence, an insulating layer pattern 11 a inclusive of the via-holes80 a is formed.

[0015] In the step 4, an electrically conductive resin is buried intoeach via-hole to form a via 8 a. A second layer wiring pattern 20 b isformed on this via 8 a by a semi-additive process, for example. Thesemi-additive process is the method of forming an electrolytic platingby applying electroless copper plating to the entire surface, forming awiring pattern by using a plating resist and growing electroplating ononly the wiring portion by using the exposed chemical copper platingfilm as an electrode.

[0016] In the step 5, the first insulating layer 1 b as the second layeris formed uniformly by the same method as that of the step 1, andpre-baking is conducted, when necessary. In the step 6, the ultra-violetrays 70 b are irradiated for exposure with the photo-mask 60 b in thesame way as in the step 2. In the step 7, the first insulating layer 1 bas the second layer is developed in the same way as in the step 3,forming the via-holes 80 b of the second layer. In the step 8, theelectrically conductive resin is buried in the same way as in the step 4to form a via 8 b. Electroless plating and electroplating are carriedout serially to complete the wiring pattern 20 c of the third layer.

[0017] A series of the process steps described above form the via-on-viastructure. The size of the via-holes or the lands is the same for eachlayer, and two lines are formed between the land and the land.

[0018] The process described above uses photolithography for forming thevia-holes, but it is also possible to form the via-holes in theinsulating layer 1 by irradiating an excimer laser or a YAG laserwithout using the mask.

[0019] As the semiconductor devices mounted onto the multi-layeredwiring board are required to possess higher functions, the number ofinput/output pins provided to the semiconductor devices and eventually,the number of lines necessary for a wiring pattern, increasesdrastically.

[0020] The number of lines that can be extended between lands becomesgreater when the size of via-holes (or lands) is smaller if the pitchbetween the via-holes (or the lands) is constant. Therefore, manyattempts have been made to reduce the size of the via-holes. Theconventional method of forming the via-holes involves the resolutionlimit of a photolithography process or the restriction by an irradiationdiameter of a laser beam spot, and never satisfactorily miniaturize thevia-holes. In consequence, a greater number of lamination is requiredfor the multi-layered wiring board and the production cost soars.

SUMMARY OF THE INVENTION

[0021] The object of the present invention is to provide a method ofproducing a multi-layered wiring board with via-holes formed free fromthe resolution limit of a photolithography process and the restrictionby an irradiation diameter of a laser beam spot.

[0022] The method of producing a multi-layered wiring board according tothe present invention comprises the step of subjecting thephotosensitive resin to exposure- and development-treatment to form theholes having a predetermined size and shape, the step of depositing andforming the curable resin to the insulating layer having the holesformed therein in such a manner as to bury the holes, and conductingheat-treatment to form the cured thin film of the curable resin on thesurface of the insulating layer, and the step of so removing the curableresin as to leave the cured thin film to acquire the via-holes havingthe reduced opening size by the cured thin film. Therefore, the methodof producing a multi-layered wiring board according to the presentinvention is capable of controlling the size of the via-holesaccurately.

[0023] The method of producing a multi-layered wiring board according tothe present invention may use an epoxy resin, an epoxy-modified acrylateresin, a cationic polymerization product of an epoxy resin, a phenolresin, a melamine resin, a carboxy-modified epoxy acrylate and acinnamate, for the photosensitive resin.

[0024] The method of producing a multi-layered wiring board according tothe present invention may use a water-soluble material such as awater-soluble resin or a water-soluble cross-linking agent for a curableresin.

[0025] The method of producing a multi-layered wiring board according tothe present invention may use those materials which are soluble inorganic solvents, such as a polymethylsiliceous siloxane, a melamineresin, an acrylate resin, an epoxy resin, and so forth, for a curableresin.

[0026] By the method of producing a multi-layered wiring board accordingto the present invention, the reduction degree of the via-hole size ofthe upper stages is greater than that of the via-hole size of the lowerstages. Therefore, the number of lines that are extended between thelands may be increased in the upper stages.

[0027] By the method of producing a multi-layered wiring board accordingto the present invention, the curable resin may contain the particles ofcalcium carbonate or polybutadiene rubber. Therefore, the adhesionstrength of the conductor pattern is improved.

[0028] By the method of producing a multi-layered wiring board accordingto the present invention, the curable resin may contain the rubberparticles having the butadiene-acrylonitrile copolymer. Therefore, theadhesion strength of the conductor pattern is improved by the chemicaltreatment.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029]FIG. 1 is a process flowchart useful for explaining a formationmethod of via-holes the size of which is reduced, according to thepresent invention;

[0030]FIG. 2 shows molecular and chemical structural formulae ofwater-soluble resins used for a second insulating layer in the presentinvention;

[0031]FIG. 3 shows molecular and chemical structural formulae ofwater-soluble cross-linking materials used for the second insulatinglayer in the present invention;

[0032]FIG. 4 is a process flowchart useful for explaining a formationmethod of via-on-via in the present invention;

[0033]FIG. 5 is a process flowchart useful for explaining a formationmethod of the multi-layered wiring board used in Example 6;

[0034]FIG. 6 shows the basic shape of a core substrate;

[0035]FIG. 7 shows sectional structures of Evaluation Boards A and Bwhose electric properties, and the like, are measured; and

[0036]FIG. 8 is a process flowchart useful for explaining a formationmethod of a via-on-via structure according to the photo via-holeprocess.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] The present invention will be explained in detail with referenceto embodiments thereof shown in the accompanying drawings. FIG. 1explains the process for forming via-holes having a reduced aperturediameter as the basis of the present invention.

[0038] Referring to FIG. 1, reference numeral 1 denotes a firstinsulating layer made of a photosensitive resin that generates reactioncomponents such as acids and radicals upon irradiation of light.Reference numeral 2 denotes a second insulating layer made of a curableresin that generates the cross-linking reaction with reaction componentssuch as the acids and radicals upon heat-treatment. Reference numeral 3denotes a core substrate on which a wiring pattern 20 having lands 50and lines 40 is formed. Reference numeral 4 denotes a cross-linked layergenerated as a result of the reaction in the interface between theinsulating layer 1 and the insulating layer 2. Reference numeral 11denotes an insulating pattern that is obtained after the exposure anddevelopment of the first insulating layer 1 and on which holes 90 areformed.

[0039] In the step 1, the first insulating layer 1 is formed to auniform thickness of 5 to 70 μm, for example, on the core substrate 3 bymeans such as spin coating, curtain coating, dip-coating, spray coating,or the like. Heat-treatment (pre-baking) is then carried out at 70 to150° C. for 1 to 60 minutes to evaporate away an excessive solventcontained in the first insulating layer 1.

[0040] In the step 2, ultra-violet rays are irradiated to the firstinsulating layer 1 with a photo-mask 60 to expose this first insulatinglayer 1. In this embodiment, the first insulating layer 1 uses aphotosensitive negative type resist. Therefore, the reaction componentssuch as acids and radicals occur at the portion irradiated with theultra-violet rays 70, forming the cross-linked structure.

[0041] In the step 3, the first insulating layer 1 is developed. Whenthe first insulating layer 1 is washed with a developing solution, theportions of the insulating layer 1 to which the ultra-violet rays 70 arenot irradiated are dissolved away, leaving thereby holes 90.Consequently, an insulating layer pattern 11 is formed, but the reactioncomponents such as acids and radicals remain at the end portions of theinsulating layer pattern 11.

[0042] The present invention may employ carbon dioxide gas (CO₂) laser,YAG laser, excimer laser, etc, for opening the holes because thereaction components such as acids and radicals occur on the irradiatedend portions of the insulating layer pattern 11.

[0043] In the step 4, the second insulating layer 2 is formed uniformlyby the same method as that of the first insulating layer 1. Next, theresulting insulating layer 2 is pre-baked at 85° C. for about 30minutes, for example, when necessary.

[0044] In the step 5, heat-treatment is carried out at a temperature,that does not invite deformation of the insulating layer pattern 11,such as at 85 to 160° C., for example. This heat-treatment diffuses thereaction components such as acids and radicals remaining in theinsulating layer pattern 11 into the second insulating layer 2. Whendiffusion of the acids and the radicals is thus promoted, thecross-linking reaction starts occurring in the interface between theinsulating layer pattern 11 a and the second insulating layer 2. Theheat-treatment time in this case is from 1 to 60 minutes, for example,and varies depending on the kind of the materials used for theinsulating layers and depending on the desired thickness of thecross-linked layer.

[0045] As a result, the cross-linked layer 4 is formed in the interfacebetween the first insulating layer 1 and the second insulating layer 2in such a manner as to cover the insulating layer pattern 11. Thecross-linked layer 4 is also called the cured resin layer.

[0046] In the step 6, washing is conducted. This washing treatmentwashes away the portions of the second insulating layer 2 that are notcross-linked. A washing solution that dissolves the non-cross-linkedportions of the insulating layer 2 but does not dissolve the insulatinglayer 1 is selected from among pure water, an aqueous solution oforganic solvents, tetramethylammonium hydrate (TMAH), alkalinedeveloping solutions such as sodium hydroxide, organic solvents, and soforth. As a result, via-holes 80 are formed.

[0047] In the step 7, the conductive resin is applied in such a manneras to bury a conductor in the via-holes 80 and to form the via 8.

[0048] The via 8 (and the via-hole 80) formed in this way has a width(diameter) smaller than the size expected by the pattern of thephoto-mask 60.

[0049] The present invention reduces the size of the via-holes byutilizing the cross-linking reaction occurring between the firstinsulating layer and the second insulating layer. Therefore, the presentinvention is free from the resolution limit of the photolithographyprocess and the restriction by the irradiation diameter of the laserbeam spot. In other words, the resolution limit in the present inventionexceeds drastically the resolution limit of the conventional methods,and via-holes having sizes by far smaller than in the conventionalmethods can be formed with high accuracy.

[0050] The reaction components such as acids and radicals are presumablyinvolved in the cross-linking reaction occurring between the firstinsulating layer and the second insulating layer. The followingreferences put the description that suggests such a view.

[0051] (a) Model of Acid Generation:

[0052] “Molecule Design of VLSI Resist”, Yuzuru Tsuda, p58, 1990,Kyoritsu Shuppan Co.

[0053] (b) Model of Radical Generation:

[0054] “Sensitizer”, edited by Katsumi Tokumaru, p154, 1987, Kodansha K.K.

[0055] The present invention is not limited to the cross-linkingreaction induced by the acids and the radicals. Needless to say, thepresent invention provides similar effects by other reaction componentsso long as the reaction utilizes the reaction components due to theincidence of the light and the cross-linking reaction or the settingreaction induced by such reaction components.

[0056] Next, concrete materials that may be applied to the first andsecond insulating layers of the present invention will be explained.

[0057] The first insulating layer uses those materials which generatethe reaction components such as acids and radicals by the irradiation oflight or by a suitable heat-treatment. In the case of photo-resists, thenegative type or the positive type can be selected appropriately. Theform of the material such as a liquid material or a film does not limitthe present invention.

[0058] Examples of the materials include a material consisting of anepoxy resin or an epoxy-modified acrylate resin as a principalcomponent, a material utilizing cationic polymerization of an epoxyresin, a material having a phenol resin and a melamine resin, or amaterial having their mixture. A material having a mixture of acarboxy-modified epoxy acrylate and an epoxy resin, and a materialhaving a cinnamate and an epoxy resin may be also used.

[0059] In contrast, the second insulating layer 2 uses those materialswhich are insolubilized in the developing solution upon heat-treatmentin the presence of the cross-linking reaction components such as acidsand radicals. A wide variety of materials such as water-soluble resins,water-soluble cross-linking agents, and water-insoluble insulatingmaterials that are soluble in organic solvents are included. Suitablematerials can be selected from among them. The form of the material suchas the liquid or the film is in no way restricted as in the case of thefirst insulating layer.

[0060]FIG. 2 shows the water-soluble resins that may be used in thepresent invention. Particularly effective among them are a polyacrylicacid, a polyvinyl acetal, a polyvinyl pyrrolidone, a polyethyleneimine,a polyethylene oxide, a styrene-maleic acid copolymer, a polyvinylamineresin, a polyallylamine, and an oxazoline group-containing water-solubleresin.

[0061] Water-soluble melamine resins, water-soluble urea resins,water-soluble alkyd resins and sulfonamide resins may be also used.

[0062] These water-soluble resins need not be used alone, and theirmixtures may be used appropriately.

[0063]FIG. 3 shows the water-soluble cross-linking agents that can beused in the present invention. They include urea type cross-linkingagents such as urea derivatives, alkoxymethylurea, N-alkoxyethyleneurea,ethyl eneurea and ethyleneureacarboxylic acid, melamine typecross-linking agents such as melamine derivatives andalkoxymethylmelamine derivatives, benzoguanamine, glycoluril, and thelike. These cross-linking agents are used either alone or as a mixture.

[0064] Though the amino type cross-linking agents are illustratedhereby, they are not restrictive, in particular. Those cross-linkingagents which generate the cross-linkage with the reaction components ofthe first insulating layer upon heat-treatment can be used for thepresent invention.

[0065] The present invention can use the water-soluble resin incombination with the water-soluble cross-linking agent in mixture. Whenused alone, some water-soluble cross-linking agents fail to form auniform coating film. Therefore, film formation performance is improvedwhen such cross-linking agents are mixed appropriately with thewater-soluble resin.

[0066] Since their mixture has high water solubility, shelf life can beimproved. When the polyvinyl acetal resin as a water-soluble resincomposition is mixed with methoxymethylolmelamine or ethyleneurea as thewater-soluble cross-linking agent, the mixture can be used stably evenafter it is preserved for a long time.

[0067] Examples of the water-insoluble insulating materials that aresoluble in organic solvents and are used for the second insulating layer2 include polymethylsiliceous siloxane, melamine resins, acrylateresins, epoxy resins, and so forth.

[0068] In this case, selection of the solvent for dissolving the secondinsulating layer is of importance. The solvent is preferably the onethat dissolves the second insulating layer but does not dissolve thefirst insulating layer and allows it to swell appropriately.

[0069] Examples of such solvents include xylene, anisole,tetrahydrofuran, N-methylpyrrolidone, γ-butyrolactone, MEK (methyl ethylketone), and so forth. These solvents can be used either alone or inmixture.

[0070] It is possible to mix inorganic particles such as calciumcarbonate or resin particles such as polybutadiene rubber particles withthe second insulating layer. It is further possible to first mixbutadiene-acrylonitrile copolymer rubber particles to form theinsulating layer, and then to conduct chemical etching by an oxidizercontainig a mixture of potassium dichromate and sulfuric acid. Becausethe surface of the insulating layer gets roughened in this way, adhesionwith the conductor can be improved.

[0071] Next, the method of controlling the cross-linking reaction willbe explained. The controlling method includes means that regulates theprocess condition and means that adjusts the material composition of thesecond insulating layer 2.

[0072] The means (1) that regulates both heat-treatment temperature andtreatment time is effective in process condition control. As thetreatment time is regulated while the heating temperature is keptconstant or as the heating temperature is regulated while the heatingtime is kept constant, the thickness of the cross-linked layer can becontrolled accurately.

[0073] From the aspect of the material composition used for the secondinsulating layer, the means (2) that mixes two suitable kinds ofwater-soluble resins and regulates the mixing ratio to control thereactivity with the first insulating layer, and the means (3) that mixesa suitable water-soluble cross-linking agent with the water-solubleresin and regulates the mixing ratio to control the reactivity with thefirst insulating layer, are effective.

[0074] The controlling condition of these cross-linking reactions mustbe determined taking various factors such as those listed below intoconsideration:

[0075] (1) reactivity of the second insulating layer with the firstinsulating layer;

[0076] (2) pattern shape and thickness of the first insulating layer;

[0077] (3) required thickness of the cross-linked layer;

[0078] (4) exposure condition and heat-treatment condition that can beemployed; and

[0079] (5) coating condition.

[0080] The material composition of the first insulating layer influencesparticularly the reactivity between the first and second insulatinglayers. When the present invention is executed in practice, the materialof the second insulating layer is optimized preferably in considerationof the factors described above.

[0081] Next, a production method of a multi-layered wiring boardaccording to the present invention will be explained with reference toFIG. 4. In the first step 1, a first insulating layer 1 a is depositedonto a core substrate 3. In the next step 2, ultra-violet rays 70 a areirradiated to the first insulating layer 1 a by using a photo-mask 60 a.In the step 3, the first insulating layer 1 a is developed and a firstinsulating layer pattern 11 a having via-holes 80 a is formed.

[0082] In the step 4, an electrically conductive resin is applied tobury the holes, and a conductor layer is formed inside each via-hole. Asecond wiring pattern 20 b is then formed by a semi-additive method, forexample.

[0083] In the step 5, a first insulating layer 1 b as the second layeris applied. In the step 6, ultra-violet rays 70 b are irradiated byusing a photo-mask 60 b. Development is conducted in the step 7, formingholes 90 b. Non-cross-linked insulating layers are dissolved away, andan insulating layer pattern 11 b as the second layer is formed. In thestep 8, a second insulating layer 2 b as the second layer is applieduniformly.

[0084] Heat-treatment is carried out in the step 9 to induce thecross-linking reaction in the second insulating layer 2 b in such amanner as to promote diffusion of reaction components from the firstinsulating layer 1 b and cover the first insulating layer 1 b. Thistreatment forms a cross-linked layer 4 b that is insolubilized in thedeveloping solution.

[0085] In the step 10, development is conducted to dissolve away thenon-cross-linked portions of the second insulating layer 2 b. Thistreatment provides via-holes 80 b the size of which is reduced.

[0086] In the step 11, the electrically conductive resin is applied tobury the holes, and a conductor layer is formed inside each via-hole thesize of which is so reduced. Furthermore, a wiring pattern 20 c as thethird layer is formed by the semi-additive method, for example.

[0087] Because the size of the via-hole immediately below the landformed hereby is reduced as described above, the diameter of the landcan be made smaller than that of the lower layer even when the overlayaccuracy margin of the pattern is the same as that of the second layer.Thus the space between the lands is increased, and the number of linesformed between the lands can be increased. Though two lines are formedin the first and second layers, three lines are formed in the thirdlayer.

[0088] In the step 12, a first insulating layer 1 c as the third layeris applied. In the next step 13, ultra-violet rays 70 c are irradiatedby using a photo-mask 60 c and the first insulating layer 1 c isexposed. In the step 14, the first insulating layer 1 c is developed,forming a first insulating layer pattern 11 c of the third layer havingholes 90 c. In the step 15, a second insulating layer 2 c of the thirdlayer is applied.

[0089] In the step 16, heat-treatment is conducted and a cross-linkedlayer 4 c of the third layer is formed. Heat-treatment in this case usesa higher heating temperature than the heating temperature used forforming the cross-linked layer 4 b in the step 9, or a longerheat-treatment time. In consequence, diffusion of the reactioncomponents such as acids and radicals is further promoted, and the filmthickness of the cross-linked layer becomes greater. In the step 17,development is conducted and the non-cross-linked second insulatinglayer 2 c is removed. As a result, via-holes 80 c the size of which isfurther reduced are formed.

[0090] In the step 18, the holes are buried by using the electricallyconductive resin, and a conductor layer is formed inside each reducedvia-hole. A wiring pattern 20 d of the fourth layer is formed thereon bythe semi-additive method, for example.

[0091] Since the space between the lands for the wiring pattern 20 d iswider than the space for the wiring pattern 20 c, the number of linesformed is greater than that of the third layer.

[0092] The explanation given above represents the case where two linesare formed between the lands for the first and second layer, three linesfor the third layer and four lines for the fourth layer. However, thenumber of lines can be decided appropriately in accordance with theLine/Space rule used.

[0093] The comparison FIG. 4 with FIG. 8 shows clearly the effects ofthe present invention. According to the conventional process, only up tosix lines can be extended even when the wiring pattern is formed intothe multi-layered structure of up to three layers. However, theembodiment of the present invention can form seven lines. If therequired number of lines is seven, the conventional process needs toform the fourth layer and invites the increase of the production cost.In addition, the greater becomes the number of layers, the lower becomesreliability of appliances.

[0094] If the wiring patterns are to be formed into the four-layeredstructure, the number of lines is 8 according to the conventionalprocess whereas it is as great as 11 in the present invention. If thenumber of necessary lines is 11, the conventional process requiresforming the sixth layer or in other words, it needs two more layers.

[0095] Because the present invention can increase the number ofextendable lines, the present invention can decrease the number oflayers to be laminated and can improve reliability of appliances.

EXAMPLE 1

[0096] This example examined the relationship between the diameters ofvia-holes and the heat-treatment condition.

[0097] (1) Lands and lines were formed by etching on an FR4 substrate(copper foil: 20 μm), a product of Mitsubishi Gas Chemicals Co, giving acore substrate 3. A photosensitive insulating resin, XP9500CC of ShipleyCo, utilizing cationic polymerization of an epoxy resin, was applied tothe core substrate by a curtain coating method, and was heated and driedat 90° C. for 50 minutes, giving a first insulating layer 1 having aresin film thickness of 50 μm.

[0098] Next, ultra-violet rays of 3.0 J/cm² were irradiated from a UVexposure machine (a product of USHIO Denki Co.) in the presence of aphoto-mask having a circular pattern having a 150 μm diameter. Afterheat-treatment was carried out (90° C./30 min), development wasconducted by using a 1.3 wt % aqueous solution of sodium hydroxide.There was thus obtained a first insulating layer pattern 11 having avia-hole pattern of a 150 μm diameter.

[0099] (2) Methoxymethylolmelamine/Cymel 370 (50 g), a product of MitsuiCyanamide K. K., pure water (180 g) and isopropyl alcohol (20 g) weremixed serially with Eslec KW3 (100 g), a polyvinyl acetal resin ofSekisui Kagaku K. K., and the mixture was stirred at a room temperaturefor 6 hours. To the resulting solution were added further 15 g ofbutadiene-acrylonitride copolymers having grain diameters of 5 μm and 1μm, respectively, and the mixtures were stirred at a room temperaturefor 6 hours to give a second insulating layer solution.

[0100] (3) The second insulating layer solution obtained in theparagraph (2) was applied by the curtain coating method to the coresubstrate on which the via-hole pattern having a diameter of 150 μm andformed in the paragraph (1) was formed, and was pre-baked at 80° C. for20 minutes.

[0101] Next, the heat-treatment was carried out under the threeconditions of 120° C./30 min, 130° C./30 min and 140° C./30 min,respectively, to diffuse the reaction components from the firstinsulating layer and to allow the cross-linking reaction to proceed.Furthermore, pure water spray development was conducted andnon-cross-linked portions in the second insulating layer were removed(at a spray pressure of 2 Kg/cm²).

[0102] Table 1 illustrates the diameters of the via-holes formed bythese operations. The diameter was smaller than 150 μm in all cases, andheat-treatment temperature dependence could be observed among the holediameters so obtained. In other words, when the treating time was keptfixed at 30 minutes, the hole diameters became progressively smallerwith a higher heat-treatment temperature.

[0103] (4) The substrate was immersed into, and swayed inside, anaqueous chromic acid (CrO₃) 500 g/L solution adjusted to 50° C. for 15minutes to examine the surface roughening effect. The substrate was thenimmersed in a neutralizing agent, OM950 of Shipley Co., and was washedwith water.

[0104] A copper paste, CPC-8000 of Sumitomo Bakelite Co, as anelectrically conductive resin, was buried into the via-patterns to forma via-conductor layer. A 20 μm-thick Cu layer was formed by thesemi-additive method and its peel strength (90° peel) was measured. Themeasurement value of the peel strength was 950 g/cm. It was thusconfirmed that sufficient peel strength was accomplished.

EXAMPLE 2

[0105] This example is another example that examined the relationshipbetween the diameters of via-holes and the heat-treatment condition.

[0106] (1) A photosensitive insulating film material, KS22 of JSR Co,was applied as the second insulating layer by the curtain coating methodto the core substrate having the via-hole pattern of a 150 μm diameterand obtained in the paragraph (1) of Example 1, and was pre-baked at 90°C. for 30 minutes.

[0107] Next, the heat-treatment was carried out under the conditions of110° C./10 min, 110° C./20 min, 110° C./30 min and 135° C./40 min,respectively, to diffuse the reaction components and to allow thecross-linking reaction to proceed. Pure water spray development was thenconducted, and non-cross-linked portions were removed (at a spraypressure of 2 Kg/cm²).

[0108] (2) Table 2 illustrates the diameters of the via-holes obtainedat this time. The diameter was smaller than 150 μm in all cases, andheat-treatment time dependence was observed among the resulting holediameters. In other words, when the treatment temperature was kept fixedat 110° C., the hole diameter became smaller as the treatment timebecame longer.

[0109] (3) This substrate was immersed into, and swayed inside, achromic acid aqueous solution 500 g/L adjusted to 50° C. for 15 minutes,and was immersed in a neutralizing agent, OM950 of Shipley Co. andwashed with water.

[0110] A copper paste, CPC-8000 of Sumitomo Bakelite K. K., was buriedinto the via-pattern to form a via-conductor. A 20 μm-thick Cu layer wasthen formed by the semi-additive method and its peel strength (90° peel)was measured. The measurement value was 950 g/cm. It was thus confirmedthat sufficient peel strength was accomplished.

EXAMPLE 3

[0111] This example is still another example that examined therelationship between the diameters of via-holes and the heat-treatmentcondition.

[0112] (1) A photosensitive insulating material, Probelec XB7081 of CibaGuigy, was applied to a substrate, FR4 of Mitsubishi Gas Chemical K.K.Exposure, heat-treatment and development were then carried out under themanufacturer's recommended condition to form via-holes having a diameterof 150 μm. A photosensitive inter-layer insulating material, XP9500CC ofShipley Co. was then applied by the curtain coating method, and waspre-baked at 90° C. for 30 minutes.

[0113] Next, heat-treatment was carried out under the conditions of 110°C./15 min, 120° C./15 min, 130° C./15 min and 135° C./20 min,respectively, to diffuse the radical components from the insulatinglayer pattern and to allow the cross-linking reaction to proceed in theinterface. Furthermore, pure water spray development was conducted toremove the non-cross-linked portions (at a spray pressure of 2 Kg/cm²).

[0114] (2) Table 3 illustrates the via-hole diameters obtained at thistime together with the heat-treatment conditions. The via-hole diameterswere smaller than 150 μm in all cases, and heat-treatment temperaturedependence was observed among the resulting hole diameters. In otherwords, when the treatment time was kept constant, the via-hole diametersbecame smaller when the treatment temperature was higher.

[0115] (3) The substrate was immersed into, and swayed inside, a chromicacid 500 g/L aqueous solution adjusted to 50° C. for 15 minutes, wasthen immersed in a neutralizing agent, OM950 of Shipley Co, and wasthereafter washed with water.

[0116] A copper paste, CPC-8000 of Sumitomo Bakelite K. K., was buriedinto the via-pattern. A 20 μm-thick Cu layer was formed by thesemi-additive method, and its peel strength (90° peel) was measured. Themeasurement value was 950 g/cm. It was thus confirmed that sufficientpeel strength was accomplished.

EXAMPLE 4

[0117] The example that formed a build-up type multi-layered wiringhaving four layers of wiring patterns by using the materials and theprocess of Example 2 is shown. However, a 1% aqueous solution of NaOHwas used in place of pure water spray for developing the secondinsulating layer.

[0118] (1) FIG. 5 shows the process flow. This process was fundamentallythe same as the one shown in FIG. 4, and the following description wasdirected to only the main points.

[0119] The core substrate had four lines of 50 μm L/S formed between thelands with a via-hole pitch of 800 μm.

[0120] In the step 4, the overlay accuracy margin of a pattern wasassumed as 100 μm with respect to the via-holes having a diameter of 150μm, and the land diameter was therefore set to 250 μm. Since the spacebetween the lands became 550 μm in this case, four lines were formed at50 μm L/S between the lands.

[0121] (2) The second insulating layer 2 b as the second layer washeat-treated at 110° C. for 20 minutes. After development was conducted,the aperture diameter of the via-holes was reduced to 100 μm. Theoverlay accuracy margin of the land diameter of the third layer wasassumed as 100 μm in the same way as the wiring pattern of the secondlayer, and was set to 200 μm. Since the via-hole diameter was reducedand the space between the lands became greater to 600 μm, five linescould be formed between the lands at 50 μm L/S.

[0122] The second insulating layer 2 c of the third layer washeat-treated at 135° C. for 40 minutes. After development was conducted,the via-holes were reduced to 40 μm. The overlay accuracy margin wasassumed as 100 μm, and the land diameter of the third layer was set to140 μm. Since the space between the lands became greater to 660 μm, sixlines could be formed between the lands at 50 μm L/S.

EXAMPLE 5

[0123] This example shows the influences of the rubber particles usedfor surface roughening on the dielectric constant, the heat expansioncoefficient and the peel strength of the insulating material. FIGS. 7(a)and (b) illustrate the sectional structures of the boards used forevaluation.

[0124] (1) 120 g of a 50% acrylate of a cresol novolak epoxy resin(Epicoat 180, a product of Yuka Shell K. K.), 80 g of bis-phenol A epoxyresin (E1001, a product of Yuka Shell K. K.), 30 g of diarylterephthalate, 6 g of Irgacure 907 (a product of Ciba Guigy Co.) and 100g of butyl cellosolve were mixed serially, and the mixture was stirredat a room temperature for 3 hours to give a first insulation layersolution A.

[0125] A first insulating layer solution A was prepared afresh, and 15 geach of butadiene-acrylonitrile copolymers having grain diameters of 5μm and 1 μm were mixed, respectively. The mixtures were stirred at aroom temperature for 3 hours to give a first insulating layer solution Bcontaining the rubber particle components.

[0126] (2) 50 g of a polyvinyl acetal resin (Eslec KW3, a product ofSekisui Kagaku K. K.), 150 g of ethyleneurea (MX280, a product of SanwaChemical K. K.), 280 g of pure water and 20 g of isopropyl alcohol wereserially mixed. The mixture was stirred at a room temperature for 2hours. To this solution were added 15 g each of butadiene-acrylonitrilecopolymers having grain diameters of 5 μm and 1 μm, respectively, andthe mixture was stirred at a room temperature for 6 hours to give asecond insulating layer solution.

[0127] (3) The first insulating layer solution A was applied by thecurtain coating method to three FR4 substrates (copper foil: 20 μm) ofMitsubishi Gas Chemicals K. K. Each substrate was heated and dried at80° C. for 30 minutes to form a first insulating layer having a filmthickness of 50 μm. Ultra-violet rays of 1.5 J/cm²were irradiated toeach substrate from a UV exposure machine (a product of USHIO Denki K.K.) by using a mask with a circular pattern having a diameter of 100 μm.After heat-treatment (90° C./30 min), each substrate was developed.Irradiation of the ultra-violet rays was again conducted at 1.5 J/cm²from the UV exposure machine to obtain an insulating layer having a holepattern of a diameter of 100 μm (Board A-1).

[0128] (4) The second insulating layer solution was applied by thecurtain coating method, and each substrate was pre-baked at 80° C. for20 minutes. The three FR4 substrates were heat-treated under differentheat-treatment conditions (120° C./30 min, 130° C./30 min and 140° C./30min) so that the cross-linking reaction proceeded in the interfacebetween the first and second insulating layers. Each substrate waswashed with pure water spray development (spray pressure=1.2 kg/cm²) toremove non-cross-linked portions in the insulating layer, and across-linked layer 4 was formed on the first insulating layer 11.

[0129] (5) Table 4 illustrates the examination result of therelationship between the heat-treatment condition and the via-holediameter. It could be confirmed that the higher the heat-treatmenttemperature, the smaller became the via-hole diameter. Among thesamples, the substrate having a hole pattern of a 90 μm diameter wascalled A-2 and was used for preparing an evaluation sample.

[0130] (6) For comparison, an insulating layer having a hole pattern ofa 100 μm diameter was formed from the first insulating layer solution Bon an FR4 substrate (copper foil: 20 μm), a product of Mitsubishi GasChemicals K. K., in the same way as the formation method of the BoardA-1. However, the ultraviolet rays were irradiated at 2.0 J/cm, and theresulting substrate was called the Board A-3.

[0131] (7) The Board A-2 and the Board A-3 were immersed into, andswayed inside, a chromic acid (CrO₃) 500 g/L aqueous solution adjustedto 50° C., for 15 minutes. After these boards were immersed in aneutralizing agent, OM950 of Shipley Co, they were washed with water.Furthermore, electroless plating and electroplating were carried out toform Cu having a film thickness of 20 μm, giving the Evaluation Board A(see FIG. 7(a)) and the Evaluation Board B (see FIG. 7(b)).

[0132] (8) The dielectric constant (25° C., 1 kHz) of the insulatinglayer, the thermal expansion coefficient (80° C. to 120° C.) in thevertical direction and the peel strength (90° peel) of these EvaluationBoards A and B were measured. Table 5 shows the measurement results.

[0133] The Evaluation Board A, that contained the rubber particles inonly the second insulating layer showed smaller dielectric constant andthermal expansion coefficient than the Evaluation Board B, thatcontained the rubber particles in all the first insulating layer andboth of boards had sufficient peel strengths. It was confirmed that theEvaluation Board A had superior characteristics in dielectric constantand thermal expansion coefficient.

What is claimed is:
 1. A method of producing a multi-layered wiring board comprising the steps of: forming an insulating layer made of a photosensitive resin on a substrate for forming multi-layered wiring, and exposing and developing said insulating layer to form holes having a predetermined shape; depositing a curable resin onto said insulating layer having said holes formed therein in such a manner as to bury said holes, heating said curable resin to form a cured thin film of said curable resin on the surface of said insulating layer; and removing said curable resin in such a manner as to leave said cured thin film and to form via-holes having a reduced opening size by said cured thin film.
 2. A method of producing a multi-layered wiring board according to claim 1 , wherein said photosensitive resin is at least one member selected from the group consisting of an epoxy resin, an epoxy-modified acrylate resin, a cationic polymerization product of an epoxy resin, a phenol resin, a melamine resin, a carboxy-modified epoxy acrylate, and a cinnamate.
 3. A method of producing a multi-layered wiring board according to claim 1 , wherein said curable resin comprises a water-soluble resin or a water-soluble cross-linking agent.
 4. A method of producing a multi-layered wiring board according to claim 1 , wherein said curable resin is at least one member selected from the group consisting of polymethylsiliceous siloxane, a melamine resin, an acrylate resin and an epoxy resin.
 5. A method of producing a multi-layered wiring board according to claim 1 , wherein said curable resin contains rubber particles consisting of a butadiene-acrylonitrile copolymer, and said method further comprises the step of chemically surface-roughening said cured thin film.
 6. A method of producing a multi-layered wiring board according to claim 2 , wherein said curable resin comprises a water-soluble resin or a water-soluble cross-linking agent.
 7. A method of producing a multi-layered wiring board according to claim 2 , wherein said curable resin is at least one member selected from the group consisting of polymethylsiliceous siloxane, a melamine resin, an acrylate resin and an epoxy resin.
 8. A method of producing a multi-layered wiring board according to claim 3 , wherein said curable resin contains particles of calcium carbonate or polybutadiene rubber.
 9. A method of producing a multi-layered wiring board according to claim 4 , wherein said curable resin contains particles of calcium carbonate or polybutadiene rubber.
 10. A method of producing a multi-layered wiring board including a plurality of stages of via-holes formed by repeating said process steps of claim 1 , wherein said via-holes of upper stages are so formed as to possess a greater degree of reduction than said via-holes of lower stages. 